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12:1 SINGLE-ENDED MULTIPLEXER
ICS850S1201I Features
* * * * * * *
12:1 single-ended multiplexer Nominal output impedance: 20 (VDD = 3.3V) Maximum output frequency: 250MHz Propagation delay: 2.7ns (maximum) Full 3.3V or 2.5V supply modes -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package
General Description
The ICS850S1201I is a low skew12:1 Single-ended Clock Multiplexer and is a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from IDT. The ICS850S1201I has 12 selectable single-ended clock inputs and 1 singleended clock output. The device operates up to 250MHz and is packaged in a 20 TSSOP package.
ICS
Block Diagram
CLK_SEL0 Pulldown CLK_SEL1 Pulldown CLK_SEL2 Pulldown CLK_SEL3 Pulldown CLK0 Pulldown CLK1 Pulldown
Pin Assignment
CLK8 CLK9 CLK10 CLK11 VDD CLK_SEL0 CLK_SEL1 CLK_SEL2 CLK_SEL3 OE 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 CLK7 CLK6 CLK5 CLK4 CLK3 CLK2 CLK1 CLK0 GND Q
ICS850S1201I
Q
CLK10 Pulldown CLK11 Pulldown
20-Lead TSSOP 6.50mm x 4.40mm x 0.925mm package body G Package Top View
OE Pullup
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Table 1. Pin Descriptions
Number 1 2 3 4 5 6, 7. 8, 9 10 11 12 13 14 15 16 17 18 19 20 Name CLK8 CLK9 CLK10 CLK11 VDD CLK_SEL0, CLK_SEL1, CLK_SEL2, CLK_SEL3 OE Q GND CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 Input Input Input Input Power Type Pulldown Pulldown Pulldown Pulldown Description Single-ended clock input. LVCMOS/LVTTL interface levels. Single-ended clock input. LVCMOS/LVTTL interface levels. Single-ended clock input. LVCMOS/LVTTL interface levels. Single-ended clock input. LVCMOS/LVTTL interface levels. Power supply pin.
Input
Pulldown
Clock select inputs. See Table 3. LVCMOS / LVTTL interface levels.
Input Output Power Input Input Input Input Input Input Input Input
Pullup
Output enable pin for Q output. LVCMOS/LVTTL interface levels. Single-ended clock output. LVCMOS/LVTTL interface levels. Power supply ground.
Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown
Single-ended clock input. LVCMOS/LVTTL interface levels. Single-ended clock input. LVCMOS/LVTTL interface levels. Single-ended clock input. LVCMOS/LVTTL interface levels. Single-ended clock input. LVCMOS/LVTTL interface levels. Single-ended clock input. LVCMOS/LVTTL interface levels. Single-ended clock input. LVCMOS/LVTTL interface levels. Single-ended clock input. LVCMOS/LVTTL interface levels. Single-ended clock input. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance Input Pullup Resistor Input Pulldown Resistor Output Impedance VDD = 3.3V5% VDD = 2.5V5% VDD = 3.465V VDD = 2.625V Test Conditions Minimum Typical 2 10 8 51 51 20 25 Maximum Units pF pF pF k k

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Function Tables
Table 3. Clock Input Function Table
Inputs CLK_SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CLK_SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CLK_SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CLK_SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Input Selected to Q CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 CLK9 CLK10 CLK11 Output goes LOW Output goes LOW Output goes LOW Output goes LOW
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V -0.5V to VDD + 0.5V 87.2C/W (0 mps) -65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C
Symbol VDD IDD Parameter Positive Supply Voltage Power Supply Current Output Unterminated Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 49 Units V mA
Table 4B. Power Supply DC Characteristics, VDD = 2.5V 5%, TA = -40C to 85C
Symbol VDD IDD Parameter Positive Supply Voltage Power Supply Current Output Unterminated Test Conditions Minimum 2.375 Typical 2.5 Maximum 2.625 41 Units V mA
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Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5% or 2.5V 5%, TA = -40C to 85C
Symbol VIH Parameter Input High Voltage Input Low Voltage Input High Current CLK[0:11], CLK_SEL[0:3] OE Input Low Current CLK[0:11], CLK_SEL[0:3] OE VOH VOL Output High Voltage; NOTE 1 Test Conditions VDD = 3.465V VDD = 2.625V VDD = 3.465V VDD = 2.625V VDD = VIN = 3.465V or 2.625V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V VDD = 3.465V or 2.625V, VIN = 0V VDD = 3.3V 5%, IOH = -12mA VDD = 2.5V 5%, IOH = -12mA Output Low Voltage; NOTE 1 VDD = 3.3V 5% or 2.5V 5%, IOL = 12mA -10 -150 2.6 1.8 0.5 Minimum 2 1.7 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 0.7 150 10 Units V V V V A A A A V V V
VIL
IIH
IIL
NOTE 1: Output terminated with 50 to VDD/2. See Parameter Measurement Information section. Load Test Circuit diagrams.
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C
Parameter fMAX tpLH tjit tsk(i) tsk(pp) tR / tF odc MUXISOLATION Symbol Output Frequency Propagation Delay, Low-to-High; NOTE 1 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Input Skew Part-to-Part Skew; NOTE 2, 3 Output Rise/Fall Time Output Duty Cycle; NOTE 4 MUX Isolation 20% to 80% f 200MHz f = 250MHz 155.52MHz 100 46 40 43 155.52MHz, Integration Range: 12kHz - 20MHz 1.4 0.35 175 600 500 54 60 Test Conditions Minimum Typical Maximum 250 2.7 Units MHz ns ps ps ps ps % % dB
NOTE 1: Measured from VDD/2 of the input to VDD/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined according with JEDEC Standard 65. NOTE 4: Input duty cycle must be 50%.
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Table 5B. AC Characteristics, VDD = 2.5V 5%, TA = -40C to 85C
Parameter fMAX tpLH tjit tsk(i) tsk(pp) tR / tF odc MUXISOLATION Symbol Output Frequency Propagation Delay, Low-to-High; NOTE 1 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Input Skew Part-to-Part Skew; NOTE 2, 3 Output Rise/Fall Time Output Duty Cycle; NOTE 4 MUX Isolation 20% to 80% f 200MHz f = 250MHz 155.52MHz 80 46 40 43 155.52MHz, Integration Range: 12kHz - 20MHz 1.5 0.32 195 600 600 54 60 Test Conditions Minimum Typical Maximum 250 2.7 Units MHz ns ps ps ps ps % % dB
NOTE 1: Measured from VDD/2 of the input to VDD/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined according with JEDEC Standard 65. NOTE 4: Input duty cycle must be 50%.
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Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 155.52MHz 12kHz to 20MHz = 0.35ps (typical)
SSB Phase Noise dBc/Hz
Offset Frequency (Hz)
As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment.
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Parameter Measurement Information
1.65V5% 1.25V5%
VDD
SCOPE
Qx
VDD
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V Output Load AC Test Circuit
2.5V Output Load AC Test Circuit
Par t 1 V
Qx
DD
2 Par t 2 V
DD
CLK1
Qy
2 tsk(pp)
CLK2
Q
Part-to-Part Skew
tPD2 tsk (i) V
Q
tPD1
DDO
tsk(i) = tPD2 - tPD1
2
t PW
t
PERIOD
Input Skew
x 100%
odc =
t PW t PERIOD
Output Duty Cycle/Pulse Width/Period
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Parameter Measurement Information, continued
Spectrum CLKx Q MUX_ISOL
80% 20% tR tF 80% 20%
(static) CLKy
Q
CLKx CLK_SELy
CLKy
MUX Isolation
Output Rise/Fall Time
CLK0: CLK11
VDD 2
Q
VDD 2 t
PD
Propagation Delay
Recommendations for Unused Input Pins Inputs:
CLK Inputs
For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
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Reliability Information
Table 6. JA vs. Air Flow Table for a 20 Lead TSSOP
JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 87.2C/W 1 82.9 2.5 80.7
Transistor Count
The transistor count for ICS850S1201I is: 649
Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP Table 7. Package Dimensions
All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153
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Ordering Information
Table 8. Ordering Information
Part/Order Number 850S1201AGILF 850S1201AGILFT Marking ICS0S1201BIL ICS0S1201BIL Package "Lead-Free" 20 Lead TSSOP "Lead-Free" 20 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Temperature -40C to 85C -40C to 85C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Contact Information:
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Technical Support
netcom@idt.com +480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA)
www.IDT.com
(c) 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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